-- 1 Bit ALU -- Expected Behavior: The inputs BINVERT and CIN along with the -- inputs OP1 and OP0 are used to determine whether to XOR A and -- B, NOR A and B, add A to B, subtract B from A, or test if A is -- less than B. The results of each computation are output to -- RESULT, and the carry from the full adder is in COUT. An -- additional input LESS is reserved for use later. library IEEE; use IEEE.std_logic_1164.all; entity alu1bit is -- the entity alu1bit is declared port(a,b,less,binvert,cin : in std_logic; op1,op0 : in std_logic; result,cout : out std_logic); end alu1bit; architecture behavior of alu1bit is -- alu1bit's behavior is defined component mux2x1 -- the mux2x1 component is defined port(ins1,ins0 : in std_logic; sel : in std_logic; outs : out std_logic); end component; For all: mux2x1 use entity work.mux2x1(behavior); component mux4x1 -- the mux4x1 component is defined port(inv : in std_logic_vector (3 downto 0); selv : in std_logic_vector (1 downto 0); outs : out std_logic); end component; For all: mux4x1 use entity work.mux4x1(structure); component full_adder -- the full_adder component is defined port(a,b,cin : in std_logic; sum,cout : out std_logic); end component; For all: full_adder use entity work.full_adder(behavior); -- The intermediate signals are declared and their types enumerated signal aNot,bNot,s0,s0Not,t0,t1,o0,o1,o2,o3 : std_logic; signal vectorinv : std_logic_vector (3 downto 0); signal vectorsel : std_logic_vector (1 downto 0); begin aNot <= not a after 1 ns; bNot <= not b after 1 ns; vectorinv(0) <= o0; -- This will store the result of XOR vectorinv(1) <= o1; -- This will store the result of NOR vectorinv(2) <= o2; -- This will store the result of the full adder vectorinv(3) <= o3; -- This will store the reserved variable less vectorsel(0) <= op0; vectorsel(1) <= op1; bmux : mux2x1 port map(bNot,b,binvert,s0); -- The 2x1MUX is defined fulladdr: full_adder port map(a,s0,cin,o2,cout); -- The full_adder is defined selmux : mux4x1 port map(vectorinv,vectorsel,result); -- The 4x1MUX is defined s0Not <= not s0 after 1 ns; t0 <= a nand s0Not after 2 ns; t1 <= s0 nand aNot after 2 ns; o0 <= t0 nand t1 after 2 ns; -- This is the result of XOR o1 <= a nor s0 after 2 ns; -- This is the result of NOR o3 <= less; -- This is the reserved less signal end behavior;