-- 1 Bit ALU (Most Significant Bit)
-- Expected Behavior: Very similar to the regular 1 Bit ALU, but
--   with a few changes. Instead of outputting the carry as COUT,
--   it is used instead with CIN to check for overflow, setting
--   OVERFLOW to 1 if it occurs. The results of the full adder are
--   assigned to SET as well as to the 3rd input inside the device.

library IEEE;
use IEEE.std_logic_1164.all;

entity alu1bit_s is                        -- the entity alu1bit_s is declared
port(a,b,less,binvert,cin : in std_logic;
     op1,op0 : in std_logic;
     result,set,overflow : out std_logic);
end alu1bit_s;

architecture behavior of alu1bit_s is      -- the behavior of alu1bit_s is defined

component mux2x1                           -- the mux2x1 component is defined
port(ins1,ins0 : in std_logic;
     sel : in std_logic;
     outs : out std_logic);
end component;

For all: mux2x1 use entity work.mux2x1(behavior);

component mux4x1                           -- the mux4x1 component is defined
port(inv : in std_logic_vector (3 downto 0);
     selv : in std_logic_vector (1 downto 0);
     outs : out std_logic);
end component;

For all: mux4x1 use entity work.mux4x1(structure);

component full_adder                       -- the full_adder component is defined
port(a,b,cin : in std_logic;
     sum,cout : out std_logic);
end component;

For all: full_adder use entity work.full_adder(behavior);

-- The intermediate signals are defined.
signal aNot,bNot,s0,s0Not,t0,t1,o0,o1,o2,o3,cout,cinNot,coutNot,of0,of1 : std_logic;
signal vectorinv : std_logic_vector (3 downto 0);
signal vectorsel : std_logic_vector (1 downto 0);

begin
  aNot <= not a after 1 ns;
  bNot <= not b after 1 ns;

  cinNot <= not cin after 1 ns;
  coutNot <= not cout after 1 ns;

  bmux : mux2x1 port map(bNot,b,binvert,s0);            -- 2x1 mux is defined
  fulladdr: full_adder port map(a,s0,cin,o2,cout);      -- full_adder is defined
  selmux : mux4x1 port map(vectorinv,vectorsel,result); -- 4x1 mux is defined

  s0Not <= not s0 after 1 ns;

  t0 <= a nand s0Not after 2 ns;
  t1 <= s0 nand aNot after 2 ns;

  o0 <= t0 nand t1 after 2 ns;
  o1 <= a nor s0 after 2 ns;
  o3 <= less;

  vectorinv(0) <= o0;       -- This will store the result of XOR
  vectorinv(1) <= o1;       -- This will store the result of NOR
  vectorinv(2) <= o2;       -- This will store the result of the full_adder
  vectorinv(3) <= o3;       -- This will store the reserved variable less

  vectorsel(0) <= op0;
  vectorsel(1) <= op1;

  set <= o2;                -- Set should be the output of the full_adder

  of0 <= cin nand coutNot after 2 ns;
  of1 <= cout nand cinNot after 2 ns;
  overflow <= of0 nand of1 after 2 ns;  -- If overflow exists, output 1, otherwise output 0
  
end behavior;