-- 32 Bit ALU
-- Expected Behavior: Three one bit opcodes, OP2, OP1, and OP0
--   determine which test to perform on the two inputs A and B.
--   The results of the chosen test are stored in RESULT, and
--   if the full_adder generates overflow, the OVERFLOW flag
--   is set to 1. If RESULT is zero, the ZERO flag is set to 1.

library IEEE;
use IEEE.std_logic_1164.all;

entity alu32bit is                        -- the entity alu32bit is declared
port(a,b : std_logic_vector(31 downto 0);
     op2,op1,op0 : in std_logic;
     result : out std_logic_vector(31 downto 0);
     zero,overflow : out std_logic);
end alu32bit;

architecture behavior of alu32bit is      -- the behavior of alu32bit is defined

component alu1bit                         -- the component alu1bit is defined
port(a,b,less,binvert,cin : in std_logic;
     op1,op0 : in std_logic;
     result,cout : out std_logic);
end component;

For all: alu1bit use entity work.alu1bit(behavior);

component alu1bit_s                       -- the component alu1bit_s is defined
port(a,b,less,binvert,cin : in std_logic;
     op1,op0 : in std_logic;
     result,set,overflow : out std_logic);
end component;

For all: alu1bit_s use entity work.alu1bit_s(behavior);

component detect0                         -- the component detect0 is defined
port(input : in std_logic_vector(31 downto 0);
     output : out std_logic);
end component;

For all: detect0 use entity work.detect0(behavior);

signal less : std_logic := '0';           -- less should be 0 on every but the LSB
signal cout : std_logic_vector(30 downto 0);
signal set : std_logic;
signal output : std_logic_vector(31 downto 0);

begin

-- I'm not going to comment every line. The next 31 lines define
-- the 31 lesser significant bits, that is, not the MSB.

  alu1bit0 : alu1bit port map(a(0),b(0),set,op2,op2,op1,op0,output(0),cout(0));
  alu1bit1 : alu1bit port map(a(1),b(1),less,op2,cout(0),op1,op0,output(1),cout(1));
  alu1bit2 : alu1bit port map(a(2),b(2),less,op2,cout(1),op1,op0,output(2),cout(2));
  alu1bit3 : alu1bit port map(a(3),b(3),less,op2,cout(2),op1,op0,output(3),cout(3));
  alu1bit4 : alu1bit port map(a(4),b(4),less,op2,cout(3),op1,op0,output(4),cout(4));
  alu1bit5 : alu1bit port map(a(5),b(5),less,op2,cout(4),op1,op0,output(5),cout(5));
  alu1bit6 : alu1bit port map(a(6),b(6),less,op2,cout(5),op1,op0,output(6),cout(6));
  alu1bit7 : alu1bit port map(a(7),b(7),less,op2,cout(6),op1,op0,output(7),cout(7));
  alu1bit8 : alu1bit port map(a(8),b(8),less,op2,cout(7),op1,op0,output(8),cout(8));
  alu1bit9 : alu1bit port map(a(9),b(9),less,op2,cout(8),op1,op0,output(9),cout(9));
  alu1bit10 : alu1bit port map(a(10),b(10),less,op2,cout(9),op1,op0,output(10),cout(10));
  alu1bit11 : alu1bit port map(a(11),b(11),less,op2,cout(10),op1,op0,output(11),cout(11));
  alu1bit12 : alu1bit port map(a(12),b(12),less,op2,cout(11),op1,op0,output(12),cout(12));
  alu1bit13 : alu1bit port map(a(13),b(13),less,op2,cout(12),op1,op0,output(13),cout(13));
  alu1bit14 : alu1bit port map(a(14),b(14),less,op2,cout(13),op1,op0,output(14),cout(14));
  alu1bit15 : alu1bit port map(a(15),b(15),less,op2,cout(14),op1,op0,output(15),cout(15));
  alu1bit16 : alu1bit port map(a(16),b(16),less,op2,cout(15),op1,op0,output(16),cout(16));
  alu1bit17 : alu1bit port map(a(17),b(17),less,op2,cout(16),op1,op0,output(17),cout(17));
  alu1bit18 : alu1bit port map(a(18),b(18),less,op2,cout(17),op1,op0,output(18),cout(18));
  alu1bit19 : alu1bit port map(a(19),b(19),less,op2,cout(18),op1,op0,output(19),cout(19));
  alu1bit20 : alu1bit port map(a(20),b(20),less,op2,cout(19),op1,op0,output(20),cout(20));
  alu1bit21 : alu1bit port map(a(21),b(21),less,op2,cout(20),op1,op0,output(21),cout(21));
  alu1bit22 : alu1bit port map(a(22),b(22),less,op2,cout(21),op1,op0,output(22),cout(22));
  alu1bit23 : alu1bit port map(a(23),b(23),less,op2,cout(22),op1,op0,output(23),cout(23));
  alu1bit24 : alu1bit port map(a(24),b(24),less,op2,cout(23),op1,op0,output(24),cout(24));
  alu1bit25 : alu1bit port map(a(25),b(25),less,op2,cout(24),op1,op0,output(25),cout(25));
  alu1bit26 : alu1bit port map(a(26),b(26),less,op2,cout(25),op1,op0,output(26),cout(26));
  alu1bit27 : alu1bit port map(a(27),b(27),less,op2,cout(26),op1,op0,output(27),cout(27));
  alu1bit28 : alu1bit port map(a(28),b(28),less,op2,cout(27),op1,op0,output(28),cout(28));
  alu1bit29 : alu1bit port map(a(29),b(29),less,op2,cout(28),op1,op0,output(29),cout(29));
  alu1bit30 : alu1bit port map(a(30),b(30),less,op2,cout(29),op1,op0,output(30),cout(30));

-- And here's the MSB, note it has no cout and that it has an overflow output

  msbalu : alu1bit_s port map(a(31),b(31),less,op2,cout(30),op1,op0,output(31),set,overflow); 

-- VHDL doesn't like variables to be both input and output, so I used another
-- variable which was two way to make it happy

  result <= output;

-- And here is my detect0. It very politely will output a 1 if all of its
-- input bits are 0.

  detect : detect0 port map(output,zero);

end behavior;