-- Maura Dailey CSE 331
-- Clock with 300 ns cycle

library IEEE;
use IEEE.std_logic_1164.all;

entity clock is
port(o : out std_logic);
end clock;

architecture behavior of clock is
begin

clock_process:process
begin
	o <= '0', '1' after 150 ns;
wait for 300 ns;
end process clock_process;
	
end behavior;