-- Data Memory
-- Expected Behavior: 1 Bit enablers MemWrite and MemRead control whether
--   to fetch data from a provided address in the memory or to store data
--   in the provided address. Data to be written to memory is stored in
--   Write_Data, while data restored from memory is found in Read_Data.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

-- changed entity from std_logic_vector type to signed type at TA request 
entity Data_Memory is
port ( Address : in signed(31 downto 0);                -- new entity Data
       Write_Data : in std_logic_vector (31 downto 0);  -- Memory is defined
       MemWrite, MemRead : in std_logic;
       Read_Data : out std_logic_vector (31 downto 0));
end Data_Memory;
 
architecture process_behavior of Data_Memory is
-- Reduced from actual size of 2^32 locations with TA's permission
type mem_array is array(0 to 7) of std_logic_vector(31 downto 0);
 
begin
 data_memory_process : process(Address, Write_Data, MemWrite, MemRead)
 
 variable data_array : mem_array :=(   -- Initialize the memory array
 (X"00000000"),
 (X"00000001"),
 (X"00000002"),
 (X"00000003"),
 (X"00000004"),
 (X"00000005"),
 (X"00000006"),
 (X"00000007"));
 
 variable addr : integer;
 
 begin
 
 addr := conv_integer(Address);                     -- Convert Address to an
                                                    -- integer so we can access
                                                    -- the memory at that location
                                                    -- to read or write to it
 
 if MemWrite = '1' then                             -- Detect if Memory will be written to
 	data_array(addr) := Write_Data;
 end if; 
 
 if MemRead = '1' then                              -- Detect if Memory will be read from
 	Read_Data <= data_array(addr) after 200 ns;
 end if;
 
end process data_memory_process;
end process_behavior;