-- Detect 0
-- Expected Behavior: If every input is 0, the output will be 1.
--   If any of the inputs is 1, the output will be 0.

library IEEE;
use IEEE.std_logic_1164.all;

entity detect0 is                      -- the entity detect0 is declared
port(input : in std_logic_vector(31 downto 0);
     output : out std_logic);
end detect0;

architecture behavior of detect0 is    -- detect0's behavior is defined
signal s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15,t0,t1,t2,t3,t4,t5,t6,t7,u0,u1,u2,u3,v0,v1 : std_logic;

begin

  s0 <= input(0) nor input(1) after 2 ns;    -- Each input is NORed with another
  s1 <= input(2) nor input(3) after 2 ns;    -- input.
  s2 <= input(4) nor input(5) after 2 ns;
  s3 <= input(6) nor input(7) after 2 ns;
  s4 <= input(8) nor input(9) after 2 ns;
  s5 <= input(10) nor input(11) after 2 ns;
  s6 <= input(12) nor input(13) after 2 ns;
  s7 <= input(14) nor input(15) after 2 ns;
  s8 <= input(16) nor input(17) after 2 ns;
  s9 <= input(18) nor input(19) after 2 ns;
  s10 <= input(20) nor input(21) after 2 ns;
  s11 <= input(22) nor input(23) after 2 ns;
  s12 <= input(24) nor input(25) after 2 ns;
  s13 <= input(26) nor input(27) after 2 ns;
  s14 <= input(28) nor input(29) after 2 ns;
  s15 <= input(30) nor input(31) after 2 ns;

  t0 <= s0 nand s1 after 2 ns;               -- The results are then NANDed
  t1 <= s2 nand s3 after 2 ns;               -- together.
  t2 <= s4 nand s5 after 2 ns;
  t3 <= s6 nand s7 after 2 ns;
  t4 <= s8 nand s9 after 2 ns;
  t5 <= s10 nand s11 after 2 ns;
  t6 <= s12 nand s13 after 2 ns;
  t7 <= s14 nand s15 after 2 ns;

  u0 <= t0 nor t1 after 2 ns;                -- Those results are NORed
  u1 <= t2 nor t3 after 2 ns;                -- together.
  u2 <= t4 nor t5 after 2 ns;
  u3 <= t6 nor t7 after 2 ns;

  v0 <= u0 nand u1 after 2 ns;               -- Then NANDed.
  v1 <= u2 nand u3 after 2 ns;

  output <= v0 nor v1 after 2 ns;            -- Then NORed to create the output

end behavior;