-- Full Adder composed entirely of NAND and INV gates.
-- Expected Behavior: A, B, and CIN will be added together,
--   the results will be output to SUM and the carry to COUT.

library IEEE;
use IEEE.std_logic_1164.all;

entity full_adder is			-- the entity full_adder is declared
port(a,b,cin : in std_logic;
     sum,cout : out std_logic);
end full_adder;

architecture behavior of full_adder is  -- the full_adder's behavior is described
signal s0,s1,s2,aNot,bNot,s1Not,cinNot,xs0,xs1,xs2,xs3 : std_logic;
begin

  aNot <= not a after 1 ns;
  bNot <= not b after 1 ns;

  s0 <= a nand b after 2 ns;

  xs0 <= b nand aNot after 2 ns;
  xs1 <= a nand bNot after 2 ns;

  s1 <= xs0 nand xs1 after 2 ns;
  s2 <= s1 nand cin after 2 ns;

  s1Not <= not s1 after 1 ns;
  cinNot <= not cin after 1 ns;

  xs2 <= s1 nand cinNot after 2 ns;
  xs3 <= cin nand s1Not after 2 ns;

  sum <= xs2 nand xs3 after 2 ns;          -- the SUM is computed
  cout <= s0 nand s2 after 2 ns;           -- the carry is assigned to COUT

end behavior;