-- Instruction Memory
-- Expected Behavior: Address is specified to read from, instruction located
--   in the memory at that location is passed to the output Instr.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

-- Read_Addr changed from unsigned to signed type at TA's request
entity Instr_Memory is
port(Read_Addr : in signed(31 downto 0);             -- New entity Instruction
     Instr : out std_logic_vector(31 downto 0));     -- Memory is defined
end Instr_Memory;

architecture process_behavior of Instr_Memory is
-- declare a new type, mem_array, that can hold 10 words (32 bit long vectors)
type mem_array is array(0 to 9) of std_logic_vector(31 downto 0);

begin

Instr_Memory_process: process(Read_Addr)

variable code_array: mem_array := (                  -- initialize the memory array
(X"8D080010"),                                       -- lw
(X"8D090008"),                                       -- lw
(X"01095026"),                                       -- xor
(X"01095827"),                                       -- nor
(X"01096020"),                                       -- add
(X"AC0C0000"),                                       -- sw
(X"11890002"),                                       -- beq
(X"01886022"),                                       -- sub
(X"08000006"),                                       -- j
(X"00000000"));

variable addr:integer;

begin

addr := conv_integer(Read_Addr);                     -- Convert address to an integer
Instr <= code_array(addr) after 200 ns;              -- Store the data found at the specified address
                                                     --   in Instr.

end process Instr_Memory_process;
end process_behavior;