-- Main Control Unit
-- Expected Behavior: The 6 bit input code determines what values to give
--   to the bits that activate or deactivate other parts of the datapath.
--   Possible types of instructions it checks for: R-Type, Jump, Branch,
--   SW and LW.
library IEEE;
use IEEE.std_logic_1164.all;

entity maincontrol is
port(inv : in std_logic_vector(5 downto 0);             -- New entity for Main
     Jump,RegDst,ALUsrc,MemtoReg : out std_logic;       -- Control Unit is defined
     RegWrite,MemRead,MemWrite,Branch : out std_logic;
     ALUop : out std_logic_vector(1 downto 0));
end maincontrol;

architecture behavior of maincontrol is
signal r0,r1,r2,r2not,r3,regout,l0,l1,l2,l3,lwnot0,lwout,s0,s1,s2,s3,sinvnot0,sinvnot1,swout,b0,b1,b2,b2not,b3,beqnot0,beqout,j0,j1,j2,j2not,j3,jumpnot0,jumpout,alusrctemp,regwritetemp : std_logic;
begin
  r0 <= inv(5) NOR inv(4) after 2 ns;          -- R-Type Instruction Detect 
  r1 <= inv(3) NOR inv(2) after 2 ns;
  r2 <= inv(1) NOR inv(0) after 2 ns;
  r3 <= r0 NAND r1 after 2 ns;
  r2not <= NOT r2 after 1 ns;
  regout <= r2not NOR r3 after 2 ns;

  lwnot0 <= NOT inv(5) after 1 ns;             -- LW Instruction Detect
  l0 <= lwnot0 NOR inv(4) after 2 ns;
  l1 <= inv(3) NOR inv(2) after 2 ns;
  l2 <= inv(1) NAND inv(0) after 2 ns;
  l3 <= l0 NAND l1 after 2 ns;
  lwout <= l3 NOR l2 after 2 ns;

  sinvnot0 <= NOT inv(5) after 1 ns;           -- SW Instruction Detect
  sinvnot1 <= NOT inv(3) after 1 ns;
  s0 <= sinvnot0 NOR inv(4) after 2 ns;
  s1 <= sinvnot1 NOR inv(2) after 2 ns;
  s2 <= inv(1) NAND inv(0) after 2 ns;
  s3 <= s0 NAND s1 after 2 ns;
  swout <= s3 NOR s2 after 2 ns;

  beqnot0 <= NOT inv(2) after 1 ns;            -- BEQ Instruction Detect
  b0 <= inv(5) NOR inv(4) after 2 ns;
  b1 <= inv(3) NOR beqnot0 after 2 ns;
  b2 <= inv(1) NOR inv(0) after 2 ns;
  b3 <= b0 NAND b1 after 2 ns;
  b2not <= NOT b2 after 1 ns;
  beqout <= b3 NOR b2not after 2 ns;

  jumpnot0 <= NOT inv(1) after 1 ns;           -- Jump Instruction Detect
  j0 <= inv(5) NOR inv(4) after 2 ns;
  j1 <= inv(3) NOR inv(2) after 2 ns;
  j2 <= jumpnot0 NOR inv(0) after 2 ns;
  j3 <= j0 NAND j1 after 2 ns;
  j2not <= NOT j2 after 1 ns;
  jumpout <= j3 NOR j2not after 2 ns;

  RegDst <= regout;                            -- 1 if R-Type Instruction
  alusrctemp <= lwout NOR swout after 2 ns; 
  ALUsrc <= NOT alusrctemp after 1 ns;         -- 1 if LW or SW Instruction
  MemtoReg <= lwout;                           -- 1 if LW Instruction
  regwritetemp <= regout NOR lwout after 2 ns;
  RegWrite <= NOT regwritetemp after 1 ns;     -- 1 if R-Type or LW Instruction
  MemRead <= lwout;                            -- 1 for LW Instruction
  MemWrite <= swout;                           -- 1 for SW Instruction
  Branch <= beqout;                            -- 1 if Branch, otherwise 0
  ALUop(1) <= regout;                          -- 1 if R-Type, otherwise 0
  ALUop(0) <= beqout;                          -- 1 if Branch, otherwise 0
  Jump <= jumpout;                             -- 1 if Jump, otherwise 0
end behavior;