-- 2x1 MUX constructed using only NAND and INV gates. -- Expected Behavior: ins0 is selected and fed into the output -- signal outs if the sel signal is 0. If the sel signal is -- 1, outs is instead set to ins1. library IEEE; use IEEE.std_logic_1164.all; entity mux2x1 is port (ins1, ins0 : in std_logic; -- We define the mux2x1 entity sel : in std_logic; outs : out std_logic ); end mux2x1; architecture behavior of mux2x1 is -- mux2x1's behavior is described signal Tins1, Tins0, selbar : std_logic; begin selbar <= not sel after 1 ns; Tins0 <= ins0 nand selbar after 2 ns; Tins1 <= ins1 nand sel after 2 ns; outs <= Tins0 nand Tins1 after 2 ns; end behavior;