library IEEE; use IEEE.std_logic_1164.all; entity mux32x2 is port (inv1, inv0 : in std_logic_vector (31 downto 0); sel : in std_logic; outv : out std_logic_vector (31 downto 0)); end mux32x2; architecture conc_behavior of mux32x2 is signal Tinv1, Tinv0 : std_logic_vector (31 downto 0); signal selbar : std_logic; begin selbar <= not sel after 1 ns; Tinv0(0) <= inv0(0) nand selbar after 2 ns; Tinv0(1) <= inv0(1) nand selbar after 2 ns; Tinv0(2) <= inv0(2) nand selbar after 2 ns; Tinv0(3) <= inv0(3) nand selbar after 2 ns; Tinv0(4) <= inv0(4) nand selbar after 2 ns; Tinv0(5) <= inv0(5) nand selbar after 2 ns; Tinv0(6) <= inv0(6) nand selbar after 2 ns; Tinv0(7) <= inv0(7) nand selbar after 2 ns; Tinv0(8) <= inv0(8) nand selbar after 2 ns; Tinv0(9) <= inv0(9) nand selbar after 2 ns; Tinv0(10) <= inv0(10) nand selbar after 2 ns; Tinv0(11) <= inv0(11) nand selbar after 2 ns; Tinv0(12) <= inv0(12) nand selbar after 2 ns; Tinv0(13) <= inv0(13) nand selbar after 2 ns; Tinv0(14) <= inv0(14) nand selbar after 2 ns; Tinv0(15) <= inv0(15) nand selbar after 2 ns; Tinv0(16) <= inv0(16) nand selbar after 2 ns; Tinv0(17) <= inv0(17) nand selbar after 2 ns; Tinv0(18) <= inv0(18) nand selbar after 2 ns; Tinv0(19) <= inv0(19) nand selbar after 2 ns; Tinv0(20) <= inv0(20) nand selbar after 2 ns; Tinv0(21) <= inv0(21) nand selbar after 2 ns; Tinv0(22) <= inv0(22) nand selbar after 2 ns; Tinv0(23) <= inv0(23) nand selbar after 2 ns; Tinv0(24) <= inv0(24) nand selbar after 2 ns; Tinv0(25) <= inv0(25) nand selbar after 2 ns; Tinv0(26) <= inv0(26) nand selbar after 2 ns; Tinv0(27) <= inv0(27) nand selbar after 2 ns; Tinv0(28) <= inv0(28) nand selbar after 2 ns; Tinv0(29) <= inv0(29) nand selbar after 2 ns; Tinv0(30) <= inv0(30) nand selbar after 2 ns; Tinv0(31) <= inv0(31) nand selbar after 2 ns; Tinv1(0) <= inv1(0) nand sel after 2 ns; Tinv1(1) <= inv1(1) nand sel after 2 ns; Tinv1(2) <= inv1(2) nand sel after 2 ns; Tinv1(3) <= inv1(3) nand sel after 2 ns; Tinv1(4) <= inv1(4) nand sel after 2 ns; Tinv1(5) <= inv1(5) nand sel after 2 ns; Tinv1(6) <= inv1(6) nand sel after 2 ns; Tinv1(7) <= inv1(7) nand sel after 2 ns; Tinv1(8) <= inv1(8) nand sel after 2 ns; Tinv1(9) <= inv1(9) nand sel after 2 ns; Tinv1(10) <= inv1(10) nand sel after 2 ns; Tinv1(11) <= inv1(11) nand sel after 2 ns; Tinv1(12) <= inv1(12) nand sel after 2 ns; Tinv1(13) <= inv1(13) nand sel after 2 ns; Tinv1(14) <= inv1(14) nand sel after 2 ns; Tinv1(15) <= inv1(15) nand sel after 2 ns; Tinv1(16) <= inv1(16) nand sel after 2 ns; Tinv1(17) <= inv1(17) nand sel after 2 ns; Tinv1(18) <= inv1(18) nand sel after 2 ns; Tinv1(19) <= inv1(19) nand sel after 2 ns; Tinv1(20) <= inv1(20) nand sel after 2 ns; Tinv1(21) <= inv1(21) nand sel after 2 ns; Tinv1(22) <= inv1(22) nand sel after 2 ns; Tinv1(23) <= inv1(23) nand sel after 2 ns; Tinv1(24) <= inv1(24) nand sel after 2 ns; Tinv1(25) <= inv1(25) nand sel after 2 ns; Tinv1(26) <= inv1(26) nand sel after 2 ns; Tinv1(27) <= inv1(27) nand sel after 2 ns; Tinv1(28) <= inv1(28) nand sel after 2 ns; Tinv1(29) <= inv1(29) nand sel after 2 ns; Tinv1(30) <= inv1(30) nand sel after 2 ns; Tinv1(31) <= inv1(31) nand sel after 2 ns; outv(0) <= Tinv1(0) nand Tinv0(0) after 2 ns; outv(1) <= Tinv1(1) nand Tinv0(1) after 2 ns; outv(2) <= Tinv1(2) nand Tinv0(2) after 2 ns; outv(3) <= Tinv1(3) nand Tinv0(3) after 2 ns; outv(4) <= Tinv1(4) nand Tinv0(4) after 2 ns; outv(5) <= Tinv1(5) nand Tinv0(5) after 2 ns; outv(6) <= Tinv1(6) nand Tinv0(6) after 2 ns; outv(7) <= Tinv1(7) nand Tinv0(7) after 2 ns; outv(8) <= Tinv1(8) nand Tinv0(8) after 2 ns; outv(9) <= Tinv1(9) nand Tinv0(9) after 2 ns; outv(10) <= Tinv1(10) nand Tinv0(10) after 2 ns; outv(11) <= Tinv1(11) nand Tinv0(11) after 2 ns; outv(12) <= Tinv1(12) nand Tinv0(12) after 2 ns; outv(13) <= Tinv1(13) nand Tinv0(13) after 2 ns; outv(14) <= Tinv1(14) nand Tinv0(14) after 2 ns; outv(15) <= Tinv1(15) nand Tinv0(15) after 2 ns; outv(16) <= Tinv1(16) nand Tinv0(16) after 2 ns; outv(17) <= Tinv1(17) nand Tinv0(17) after 2 ns; outv(18) <= Tinv1(18) nand Tinv0(18) after 2 ns; outv(19) <= Tinv1(19) nand Tinv0(19) after 2 ns; outv(20) <= Tinv1(20) nand Tinv0(20) after 2 ns; outv(21) <= Tinv1(21) nand Tinv0(21) after 2 ns; outv(22) <= Tinv1(22) nand Tinv0(22) after 2 ns; outv(23) <= Tinv1(23) nand Tinv0(23) after 2 ns; outv(24) <= Tinv1(24) nand Tinv0(24) after 2 ns; outv(25) <= Tinv1(25) nand Tinv0(25) after 2 ns; outv(26) <= Tinv1(26) nand Tinv0(26) after 2 ns; outv(27) <= Tinv1(27) nand Tinv0(27) after 2 ns; outv(28) <= Tinv1(28) nand Tinv0(28) after 2 ns; outv(29) <= Tinv1(29) nand Tinv0(29) after 2 ns; outv(30) <= Tinv1(30) nand Tinv0(30) after 2 ns; outv(31) <= Tinv1(31) nand Tinv0(31) after 2 ns; end conc_behavior;