-- 4x1 MUX composed using structural VHDL from 3 2x1 MUXes
-- Expected Behavior: A signal is selected from among the four
--   bits of the inv input vector. If selv is 0, the first bit
--   is selected, if selv is 1, the second, and so on.

library IEEE;
use IEEE.std_logic_1164.all;

entity mux4x1 is
port (inv : in std_logic_vector (3 downto 0);  -- We define a new entity 
      selv : in std_logic_vector (1 downto 0);
      outs : out std_logic);
end mux4x1;

architecture structure of mux4x1 is      -- mux4x1's behavior is described
signal s0,s1 : std_logic;

component mux2x1                         -- the subcomponent mux2x1 is described
port (ins1, ins0 : in std_logic;
      sel : in std_logic;
      outs : out std_logic);
end component;

for all : mux2x1 use entity work.mux2x1(behavior); -- the location of the 2x1 mux is given 

begin
  m0 : mux2x1 port map(inv(1),inv(0),selv(0),s0);  -- the first 2x1 mux is described
  m1 : mux2x1 port map(inv(3),inv(2),selv(0),s1);  -- the second 2x1 mux is described
  m2 : mux2x1 port map(s1,s0,selv(1),outs);        -- the third 2x1 mux is described
end structure;