library IEEE;
use IEEE.std_logic_1164.all;

entity mux5x2 is
	port (inv1, inv0 : in std_logic_vector (4 downto 0);
		     sel : in std_logic;
		    outv : out std_logic_vector (4 downto 0));
end mux5x2; 

architecture behavior of mux5x2 is
    signal Tinv1, Tinv0 : std_logic_vector (4 downto 0);
                 signal selbar : std_logic;
		 
begin
    selbar <= not sel after 1 ns;
    
    Tinv0(0) <= inv0(0) nand selbar after 2 ns;
    Tinv0(1) <= inv0(1) nand selbar after 2 ns;
    Tinv0(2) <= inv0(2) nand selbar after 2 ns;
    Tinv0(3) <= inv0(3) nand selbar after 2 ns;
    Tinv0(4) <= inv0(4) nand selbar after 2 ns;
    
    Tinv1(0) <= inv1(0) nand sel after 2 ns;
    Tinv1(1) <= inv1(1) nand sel after 2 ns;
    Tinv1(2) <= inv1(2) nand sel after 2 ns;
    Tinv1(3) <= inv1(3) nand sel after 2 ns;
    Tinv1(4) <= inv1(4) nand sel after 2 ns;
    
    outv(0) <= Tinv1(0) nand Tinv0(0) after 2 ns;
    outv(1) <= Tinv1(1) nand Tinv0(1) after 2 ns;
    outv(2) <= Tinv1(2) nand Tinv0(2) after 2 ns;
    outv(3) <= Tinv1(3) nand Tinv0(3) after 2 ns;
    outv(4) <= Tinv1(4) nand Tinv0(4) after 2 ns;
    
end behavior;