library IEEE;
use IEEE.std_logic_1164.all;

entity pc is
port (clock: in std_logic;
      input : in std_logic_vector(31 downto 0);
      output: out std_logic_vector(31 downto 0));
end pc;

architecture behavior of pc is
begin
pc_process: process(input,clock)

variable start : std_logic := '1';
variable pc_pointer : std_logic_vector(31 downto 0) := x"00000000";

begin

if (clock'event and clock = '0')
then
if (start = '0')
then
pc_pointer := input;
else
start := '0';
end if;
end if;

output <= pc_pointer;

end process pc_process;
end behavior;