library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity regfile is
  port (write_data : in std_logic_vector(31 downto 0);
	src1_addr, src2_addr, dst_addr: in unsigned(4 downto 0);
	write_cntrl: in std_logic;
	src1_data, src2_data: out std_logic_vector(31 downto 0));
end regfile;

architecture process_behavior of regfile is
  type reg_array is array(0 to 31) of std_logic_vector(31 downto 0);
begin
  regfile_process: process(src1_addr,src2_addr,write_cntrl)
  variable data_array:reg_array := (
    (X"00000000"),
    (X"00000000"),
    (X"00000000"),
    (X"00000000"),
    (X"00000000"),
    (X"00000000"),
    (X"00000000"),
    (X"00000000"),
    (X"00000000"),
    (X"00000000"),
    (X"00000000"),
    (X"00000000"),
    (X"00000000"),
    (X"00000000"),
    (X"00000000"),
    (X"00000000"),
    (X"00000000"),
    (X"00000000"),
    (X"00000000"),
    (X"00000000"),
    (X"00000000"),
    (X"00000000"),
    (X"00000000"),
    (X"00000000"),
    (X"00000000"),
    (X"00000000"),
    (X"00000000"),
    (X"00000000"),
    (X"10008000"),
    (X"7fffeffc"),
    (X"00000000"),
    (X"00000000"));

  variable addrofsrc1, addrofsrc2, addrofdst: integer;
  begin
    addrofsrc1:=conv_integer(src1_addr);
    addrofsrc2:=conv_integer(src2_addr);
    addrofdst:=conv_integer(dst_addr);

    if (write_cntrl = '1' and addrofdst /= 0) then
      data_array(addrofdst):=write_data;
    end if;

    src1_data <= data_array(addrofsrc1) after 10 ns;
    src2_data <= data_array(addrofsrc2) after 10 ns;
  end process regfile_process;
end process_behavior;